1. Field of the Invention
The present invention generally relates to a timing model. More specifically, the present invention relates to a timing model of a functional block and a method of LSI (large scale semiconductor integrated circuit) designing using the timing model.
2. Background Information
In the field of LSI systems and related devices, a method of turning a core functional block of an LSI into a module and recycling the functional block has become typical in recent years. This method has been pursued as a measure to shorten the length of time for designing an LSI and to improve productivity.
As an example of the conventional art, Japanese Patent No. 3420195, which is hereby incorporated by reference, discloses a method of LSI designing, in particular, a method of LSI layout designing using a module.
In the LSI designing using a module, logic composition, timing verification, etc. are performed using a timing model in which the timing information inside the module is incorporated. This timing information is made of input setup time, input hold time, and output delay time inside the module. In the definition of each time, clock delay time inside the module is already included. Furthermore, in the process of logic composition, pre-layout timing verification, and post-layout timing verification, the same timing model is used.
In the usual LSI designing, logic composition is performed under so-called ideal clock conditions where the delay time of a clock is assumed to be zero. However, in the timing model of the module, the propagation clock conditions which contained internal clock delay time are already defined. Therefore, when designing a higher rank class using the module, the difference between the ideal clock conditions of this higher rank class and the propagation clock conditions inside the module influences the timing restrictions greatly. For this reason, it is difficult to design an LSI with a desired performance. Then, in the logic composition, it is necessary to use another timing model set as the ideal clock conditions where the clock delay time inside the module is disregarded. This is also the same in the case of pre-layout timing verification.
On the other hand, in post-layout timing verification, i.e. the timing analysis performed after physical layout is completed, the timing model of the propagation clock conditions containing the clock delay time is needed.
However, under the present circumstances, since the timing model which fulfills ideal clock conditions and propagation clock conditions simultaneously does not exist, it is necessary to prepare two kinds of timing models according to a design step. For this reason, the design environment tends to become complicated. Moreover, there is a possibility that design efficiency might decline. In addition, Japanese Patent No. 3420195 does not indicate any designing method of LSI for solving such a problem.
In view of the above, it will be apparent to those skilled in the art from this disclosure that there exists a need for an improved a method of LSI designing and a computer program for designing LSIs. This invention addresses this need in the art as well as other needs, which will become apparent to those skilled in the art from this disclosure.